Electronic data processing machine



July 27, 1965 J. A. HADDAD ETAL ELECTRONIC DATA PROCESSING MACHINE original Filed Maron so, 1954 9 Sheets-Sheet l July 27, 1965 .1.A. HADDAD ETAL ELECTRONIC DATA PROCESSING MACHINE Original Filed March 30. 1954 9 sheets-sheet 2 July 27, 1965 J. A. HADDAD ETAL 3,197,624

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bwmvmw v July 27, 1965 J. A. HADDAD ETAL ELECTRONIC DATA PROCESSING MACHINE Original Filed March 50, 1954 IAVENTOR.. JAH/400140 nil/1.9330051 SP A wmp, www M HWP/Wm KRD .MNH MVA Y B @Si July 27, 1965 J. A HADDAD ETAL ELECTRONIC DATA PROCESSING MACHINE 9 Smets-sheet s Original Filed March 30. 1954 July 2g, 196s J. A. HADDAD ETAL 9 Sheets-Sheet 9 ACCUMULATOR REGISTER S ORDER C2) /1'0-0 #M6/6) 75310' 7654 7644 l Wax a. n S I O H T0 Aca/s) f 0R CF D @I FIG 7f ACCUMULATOR REGISTER ORDERS o, P, AND1 fnwgqn 35 How Acc a 775g Acc (N+/J @arp/fr 6 7750 ggf/Hna ,W6/17' a t f v 7,1760 77,17 C6/N) C9 neem-damour I 0R CF D @3 5 SMFQGFI e 2 60M @0r/0r a 577211 O noaa/e ro Acc 77/d INVENroRJ JAH/100,40 ,e/M/cHn/eas BY /v. @06f/65TH? Afro/P EY United States Patent Oflice 3,l97,624 Patented July 27, 1965 3,197,624 ELECTRONIC DATA PROEESSTNG MACHINE .lerrier A. Haddad, Binghamton, Richard K. Richards, Poughkeepsie, Nathaniel Rochester, Wappingers Falls, and Harold D. Ross, ir., Reughlreepsie, N.Y., assignors to International Business Machines `Corporation, New York, NX., a corporation of New York Original application Mar. 30, 1954, Ser. No. 419,642, now Patent No. 2,974,866, dated Mar. 14, 1961. vDivided and this appiication June 27, 1960, Ser. No. 42,458 18 Ciairns. (El. 235-175) The present invention relates toV a Calculator for performing binary calculations on data; derived from the cathode ray tube storage elements comprising the Memory of an Electronic Data Processing Machine. This application is a division of an application of I. A. Haddad et al., Serial No. 419,642, filed March 30, 1954, now U.S. Patent No. 2,974,866, entitled Electronic Data Processing Machine.

As set forth below, in A BRIEF OUTLINE OF THE CALCULATOR, the Calculator, per se, is operated by a Program, stored in Memory, said Program including instructions for initiating certain Arithmetical processes upon data, also stored in said Memory. The Calculator is of the parallel type comprising 35 orders and a Sign order and all 35 orders are handled, in parallel.

The Calculator, per se, comprises a 36 Order Memory Register, comprising 35 orders and a Sign order; a 35 order Adder, each comprising a full binary adder, of logical AND and OR circuits and additional circuitry and two overilow orders, each comprising half binary adders of logical AND and OR circuits and additional circuitry; an Accumulator Register, of 35 orders, for storing data, two overow orders and a Sign order, each comprising a Delay Unit, as the storing element, per se, of each order, which Unit, as described below, has the inherent faculty of emitting an output indication, of a previously stored bit, as a new bit is simultaneously applied to the input of said Unit. Another register called the Multiplier Quotient Register (MQ) comprising 35 orders and a Sign order also utilizes a Delay Unit, as the storage element, per se. The 35th order of the Accumulator Register is connective to the Multiplier Quotient 1 order and vice versa, whereby the MQ and the Accumulator Register are sbiftable, yas a unit, any desired number of steps, either to the right or to the left. As pointed out below, the logical nature of the Adder and the unique characteristic of simultaneous input and output of the Delay Units, along with the fact that the outputs of the Accumulator Register Delay Units are respectively connectedy to inputs of the Adder orders, and operable to deliver True or Complement representations of the respective values, stored in said Accumulator Register, while outputs of the respective Adder orders are respectively connected to the inputs ofthe Delay Units of the Accumulator Register, provide a Calculator wherein carries ripple through almost instantaneously and due to the simultaneous input/output feature of the Delay Units, tentative arithmetical operations can be performed and can also be completed or not completed, selectively, in accordance with operating conditions, whereby extremely rapid calculations are produced, at speeds heretofore unheard of, and limited only by the operating speeds of the circuit components, per se.

Further, Sign indicating and checking devices are provided whereby the Calculations may be performed in accordance with the Signs and including special operations particularly involving Signs, and the results of said Calculations are stored, with the proper Sign indications.

Means are provided, as stated above, to read Instructions from Memory and control data handling in accordance with these Instructions, both data and the Instructions being stored in Memory, at selectable Addresses. As described below, Instructions comprise half words of 18 bits, including Sign, read from Memory to the Memory Busses and via the Memory Busses to a Memory Register, hereinafter referred to as the MR and from the MR to an Instruction Register having a Sign storage por-tion, an Operation storage portion and an Address storage portion, which latter is also operative, as a Count Down Counter, to count the number of certain steps, during for example, MUL'I'IPLY, DIVIDE or SHIFT operaions. The Instruction Register stores binary 1 and binary zero manifestations, the permutations thereof stored in said Operation portion being DE-CODED by an Operation Decoder which, in turn, controls various Control Circuits including Execution Timers and Mixing Circuits, all as described below, whereby each of the Instructions, so de-coded, is respectively carried out.

When data comprising full or half words are read from Memory to the MR,*it may be read to the Adder and thus to the Accumulator Register.

Said Memory Register is also connective to said Multiplier Quotient Register, referred to hereinafter as the MQ to thus transfer data from Memory via the MR to said MQ. Such data, delivered to the MQ or to the Adder, as mentioned above, may comprise FULL or HALF words, a FULL Word comprising two HALF words and consisting of 35 bits and the Sign bit, all as described below.

Overflow and Carry triggers are provided to indicate when an Overliow occurs from the regular orders to the overow orders of said Accumulator Register and to indicate carries, from the highest order of said Adder and also from the highest overow order thereof. Various other circuits are provided, as described in detail below,

to provide means whereby a large number of arithmetical and data handling operations can be performed under control of Instructions stored in said Memory, and Read out, therefrom, to said various circuits, including said Operation Decoder.

Among the Operations which are performed are STOP AND TRANSFER, TRANSFER, TRANSFER ON AND RESET OVERFLOW, TRANSFER ON ZERO, ADD, RESET AND ADD, ADD ABSOLUTE VALUE, SUB- TRACT, RESET AND SUBTRACT, SUBTRACT AB- SOLUTE VALUE, NO OPERATION, STORE, STORE ADDRESS, STORE NUMBER FROM MQ, LOAD MQ, MULTIPLY, ROUND, MULTIPLY AND ROUND,

DIVIDE, LONG SHIFT LEFT, LONG SHIFT RIGHT,

SHIFT ACCUMULATOR LEFT, and SHIFT AC- CUMULATOR RIGHT.

Various other Operations are performed by said Electronic Data Processing Machine, as set forth in the copending application of Philip E. Fox et al., Serial No. 417,702, tiled March 22, 1954, now Patent No. 2,950,465, issued August 23, 1960. Still other operations, particularly those utilizing Input/Output units, such as magnetic tapes, are disclosed in the co-pending application of Bartelt et al., Serial No. 401,648, tiled December 31, 1953, now Patent No. 2,850,234, issued September 2, 1958, and in the co-pending application of Bartelt et al., Serial No. 401,502 led December 31, 1953, now Patent No. 2,921,293, issued January 12, 1960, and still other operations, particularly those utilizing Magnetic Drums, are disclosed in the co-pending application of YVerner Buchholz et al., Serial No. 316,914, filed October 25, 1952, now Patent No. 2,863,134, issued December 2, 1958.

One of the objects of the present invention, therefore,

is to provide, means for carrying out, efficiently and at alec/,aaa

high speed, certain of these operations and particularly those pertaining to Arithmetical operations.

Another object of the present invention is to provide a full binary adder comprising, in combination, a first diode OR circuit having three input-s, its output feeding to a first diode AND circuit, a second AND circuit having three inputs, its output feeding to a second diode OR circuit, said second OR circuit having an output feeding to said first AND circuit, a third diode AND circuit having two inputs and its output feeding v-ia a third diode OR circuit, to an inverter, said inverter output feeding to said second OR circuit, a fourth AND circuit having two inputs, its output feeding to said th-ird OR circuit and a fifth AND circuit having two inputs, its output feeding to said third OR circuit, said first AND circuit providing a sum output of binary l or binary 0, when binary 1 and binary 0 inputs are lapplied to the respective inputs of said other AND circuits or the respective inputs of said first OR circuit, and said third OR circuit providing a carry output, of binary l or binary 0.

Still another object is to provide a device having an object, as above, and including means selectively feeding True or Complement representations, of binary ls and binary s, of a first factor, to said first OR circu-it, and comprising one input to each of said second, third and fourth AND circuits, respectively.

A further object is to provide .a device having an object, as above, and including means for producing a carry input, to said fir-st OR circuit and comprising one input to each of said second, fourth and fifth AND circuits, respectively.

Another object is to provide a device having an object, as above, and including means providing binary l or binary 0 inputs, representative of a second factor, to said first OR circuit, and to said second, third and fifth AND circuits, respectively.

A further object is to provide a device having an object, a-s above, said True Complement input circuits compnising a first AND circuit having a True input thereto and a second AND circuit, means producing a conditioning potential for said first AND circuit, for passing said True value input therethrough to said full binary adder, means including an inverter connected to said True input and apply-ing its output to said second AND circuit to thus apply a Complement value input, and means producing a condition-ing potential for said second AND circuit, for passing said Complement value input therethrough, to said `full binary adder.

Other objects yof the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose by way of example, the principle of the invention and the best mode which has been contemplated of .applying that principle.

Since the invent-ion herein relates to an electronic data processing machine, the details of which are set out fully in the aforementioned parent application (Haddad et al. Patent No. 2,974,866), the specification herein has been largely curtailed. Specifically, the description and drawings corresponding to Haddad patent FIGURES 12a-7c and 7g-8c have been eliminated from this specification. The remaining figures herein retain their original numbering for easy cross reference to said Haddad et al. patent.

In the drawings:

FIGS. 1a, 1b, 1c, 1d, le, 1f and lg taken together, as shown in FIG. lh, comprise an overall block diagram of the Calculator.

FIG. 7d comprises a block diagram of a half adder and true complement controls representative the Adder orders P and Q.

FIG. 7e comprises a block diagram of the Sign order ofthe Accumulator Register.

FIG. 7f comprises a block diagram of an Accumulator Register order, representative of orders Q, P and 1 through 3.

3: A BRIEF OUTLNE OF THE CALCULATOR In the novel Calculator comprising this invention, words of 36 bits or half words of 1S bits are manifested or recorded in a pure binary system of notation. In such a binary notation, only two digit values exist, that is, 0 and l, and these respective binary 0 or binary 1 digits are referred to as bits. The binary point corresponding to a decimal point in a decimal system may of course, occupy any position in the pure binary word. The digital position or orders of a binary number, reading from RGHT to left, of the binary point, correspond in value to 2, 21, 22, 23, 24, 25, etc. or decimal digits l, 2, 4, 8, 16, 32 etc. respectively. The digital position or order for a binary number, reading from LEFT to right, of the binary point, correspond in value to 2 1, 2 2, 2*3, 2*'4, 25, etc., or the decimal or fractional values 1/2, 1A, 1A, V16, 1/32, %4, respectively. The novel Calculator of this invention normally performs operations, on full Words, which as stated above consisting of 36 bit-s compris-ing 35 bits (binary digits) and a sign bit. However, for economy of operation, 4any of the full words may be split into two half words, each half word as stated above, consisting of 18 bits, comprising 17 bits and a sign bit. A binary number of a full word of 36 bits has a precision equal to that of about a l0 decimal digit number, and the half word corresponds in precision to a number of about 5 decimal digits. As described below, the calculator operates according to a stored program, this program comprising instructions each of which is a half word.

The position of the binary pc-int is determined more or less by the programmer, and the arithmetic operations such as addition, subtraction, multiplication, division, and the like, must be performed according to definite rules. The programmer must keep track of the binary point position.

FIGS. la through 1g, taken together, and arranged as shown in FIG. lh, comprise an overall block diagram of an Electronic Data Processing Machine including the novel Calculator and showing, in general, the relationship of the various Units which make up this Machine. The Memory Unit as used in the machine and as illustrated by a labeled block, in FIG. lc, comprises cathode ray tubes used as electrostatic data storage means which have a maximum capacity of 2,048 full words of storage (36 bits per word). These 2,048 full words, are stored, on 36 sets, of cathode ray tubes and since any full word may be split into two half words, thet total number of half words, which can be stored, is 4,096. The number of cathode ray tubes provided, is chosen at 36, since in the novel Calculator of this invention a full word is 36 bits, so that with 36 sets of cathode ray tubes, 36 bits may be read out of the Memory Unit simultaneously or 36 may be stored, in the Memory Unit, simultaneously, during one cycle of operation. This simultaneous operation is referred to as parallel operation. The Memory Unit, employed herein is shown, described and claimed in the copending application of Philip E. Fox et al., Serial No. 417,702, filed March 22, 1954, now Patent No. 2,950,465 issued August 23, 1960.

The timing of the Calculator is controlled by a Clock which comprises a twelve stage electronic trigger ring The Clock develops 12 master timing pulses of one microsecond duration each, and a character cycle, of the Calculator, will be defined as one twelve microsecond period (one complete cycle of the Clock). The Clock is illustrated by the labeled block in FIG. lb.

There are four general types of character cycles existing the Machine operation. These four types of cycles are called Instruction, Execute, Execute/ Regenerate, and Regenerate cycles, which are respectively abbreviated as I, E, E/R and R. The type of cycle at any certain time is controlled by a Cycle Timer, also illustrated by a labeled block in FIG. lb.

As set forth in said above identified copending appli cation of Fox et al., the electrostatic storage which comprises Mernory for the Machine may be addressed, and the information, stored in Memory, at the respective addresses, may be read out to a Memory Register. All information leaving the Memory Units, enters this Memory Register which comprises 36 Delay Units, S, and 1 through 35, inclusive, each of the type as described below, along with associated switching circuits. The Memory Register designated hereinafter as MR, functions as a buler storage between Memory and the Computer. The 36 Delay Units of this MR provide storage for 36 bits read from Memory and hold these bits until they are called for by the Calculator. Information is read, out of Memory into the MR, in parallel fashion, that is, 36 bits are read, simultaneously, for a full word, or 18 bits, simultaneously, for a half word. If 36 bits are read they are read into all 36 Delay Units of MR but if a half word is read, they are always rea-d into the Delay Units S, and 1 through 17 of the MR. Information thus read into the MR may not only be transferred to the Calculator but also via a Register of the Calculator, described presently, to other Units of the Machine. The Adder (FIG. ld) represented by labeled blocks, comprises 37 columnar orders, two, of which, are overow columns P and Q. Each of the columnar orders 1 through 35 of the Adder consists of a group of circuits, as described in detail later, comprising three inputs, and two outputs.

The three inputs are (l) an output from a corresponding column of the MR; (2) an output from a corresponding column of an Accumulator Register described below; (3) a carry output from the Adder columnar order to the right.

The two outputs are: (l) the sum output; (2) a carry output. The sum output is fed to a corresponding column of the Accumulator Register, while the carry output goes, to the Adder column, to the left. In conjunction with means for controlling the flow of information, the Adder circuitry` performs the functions of addition, subtraction, multiplication and division, all as described presently, multiplication and division consisting of a series of additions or subtractions and shifts, so that multiplication and division are also performed, in part, by the Adder circuitry. The Adder is not a register, per se, and therefore does not perform any function of storage, but merely operates, on the information as it is passed therethrough.

The Accumulator Register is used for storing the output of the Adder, and the combination, of the Adder and the Accumulator Register, may be regarded as an Accumulator. The Accumulator Register stores the results, of the operation performed, by the Adder. It consists of 38 columns, 2 of which, namely, Q and P, are for the purpose of overilow, and the other 36 comprising the 35 binary bits, of a full word, and the sign. Each of the columns of the Accumulator Register consists of a Delay Unit, similar to that used in the MR and the contents of the Accumulator Register may be shifted, either to the left or the right. The contents of the Accumulator Register, excluding the contents, of the overflow columns, may be stored, in Memory, by a STORE Instruction, which is given with a Memory address. In this STORE operation, the number is stored, in Memory, andthe same number is left unaltered in the Accumulator Register.

The Multiplier Quotient Register, hereinafter referred to, as the MQ has two major functions. Gne, as its name implies, it holds the Multiplier, for multiplication operations and the Quotient, in division operations. The MQ 4 comprises 36 columns, one, of which, stores a manifestation of the sign of the number stored in the MQ, the remaining 35 columns storing manifestations of the multidigit number itself. Each column contains a Delay Unit, of the type used in the MR, along with suitable switching circuits. Words may be read, from Memory, via the MR into the MQ register by means of a LOAD MQ Instruction, which includes a Memory address, and the contents of the MQ may be read out, and via Memory Bus Switches, be stored in Memory, by means of a STGRE MQ Instruction which includes a Memory address. These Memory Bus Switches are illustrated in FIG. le, and are effective, as described below, to switch the holding of the Accumulator Register to the Memory Busses, for either full or half words, during a STORE. Instruction, or to shift the contents of the MQ, either full or half words, to the Memory Busses, during a STRE MQ Instruction.

rIlle Instruction Register (FIG. 1f) which may receive information from the MR, serves as a storage Register for an Instruction (a half word) read, from Memory, during an Instruction cycle. The Instruction Register stores the coded binary bit representation, of a particular Instruction, until this Instruction is completely executed, and it is then reset, during the early part of the next Instruction cycle, before a new Instruction, is read, into it from Memory. Thus, the Instruction Register holds the complete Instruction and the Operation part, of this Instruction is available to an Operation Decoder (FIG. 1f) until the particular operation is complete, while the Address portion of the Instruction, is available to a Deiiection Register (FIG. le) as described below. 'This Deiiection Register comprises a plurality of electronic triggers, each, respectively storing a binary bit representation, of the sign bit, and also of bits 6 through 17, inclusive. An Address Counter portion, of the Instruction Register, is utilized during multiply and divide operations, for the purpose of counting the number of cycles that the Machine completes, during the respective such operations. The purpose of this counter is to insure that a proper number of character cycles occurs, during each of these operations.

The Instruction Counter (FIG. 1e) is a 12 stage counter, each stage comprising an electronic trigger, the Counter output being fed to the Deflection Register during each Instruction cycle. The Instruction Counter receives a pulse at the END of each Operation so that on the next Instruction cycle, a succeedingly numbered address in Memory, will be referred to. The Instruction Counter may under certain conditions, also Vbe stepped to cause a skipping of Instructions.

The Regeneration Counter (FIG. 1e comprises ten stages each including an electronic trigger, respectively storing binary bit representations of the bits 6 through l5, inclusive. The Regeneration Counter output, is fed to the Deiiection Register during Execute/Regenerate and during Regenerate cycles and is stepped, one count, for each such cycle so that succeeding numbered addresses, in Memory, are addressed and Regenerated, during successive EXecute/Regenerate and Regenerate cycles.

The Deflection Register has l2 orders, each comprising an electronic trigger, whose outputs feed to the Memory Detiection circuits andthe Memory Control circuits. This Deflection Register therefore serves as a buffer between the Instruction Register, the Instruction Counter and the Regeneration Counter, on one hand and the Memory Deflection circuits and the Memory Control circuits, on the other hand. The Memory Deflection 1 and Memory Control circuits, represented by the labeled block in FIG. 1g, are identical to those described in detail in said above identified Fox et al, application are effective to ADDRESS and UNBLANK the respective cathode ray tubes comprising Memory for both READING out of or WRITING in Memory.

The Operation Decoder decodes the manifestations of the l to 5 bit permutations which comprise the Operation part, of the Instruction to determine which one, of 32 possible Instructions, the machine will perform. The Operation Decoder comprises a diode matrix circuit and receives these permuted inputs and produces one output only, of any one of 32, thus signalling the particular kind of operation that is to be performed. The Operation De- 7 thus engaged, conditions selectively, various control circuits, which in turn produce the respective type of operation called for.

The information stored in Memory, is categoried into two general classes, according to the purpose for which it is used. These are Instructions and numerical information which is to be processed in accordance with the particular Instruction. The Calculator is made to distinguish between Instructions and numerical information by the selected type of cycle, causing Reading from memory. Information Read-out of Memory, during an Instruction cycle is CHANNELED to the Instruction Register where the stored manifestations of the bits Read- Out comprises a representation of the Instruction. Information Read-out during an Execute cycle, is handled as numeric data. Numeric data is available, either in half words of 'i8 bits or in full words of 36 bits, but Instructions are ALWAYS half words. The Gate Generator, illustrated in FIG. 1b, controls the basic timing of the machine and provides signals which are used in the respective operations, as described later. The Address, Sign, and Address Counter Mixer circuits illustrated by a labeled block in FIG. lb combine the outputs from the Sign bits, of the MR, the Accumulator Register, and the MQ, to provide signals indicating that the Signs, are alike or unlike, and also passes signals, from the Instruction Register indicating when the Address Counter reaches a desired count during a multiply or a divide operation and whether a full, an even half or an odd half word is addressed. Outputs from these circuits feed to the Execution Timer and to the Mixing circuits.

A carry trigger is utilized to supply an indication that an end carry has occurred from the Q position of the Adder during certain operations. An Overtiow trigger is utilized to supply an indication that a carry has occurred from the Adder l position to the overflow position P during Vcertain operations or that a binary 1 has been shifted left from the Accumulator Register l position to the Accumulator Register P position during other operations.

The Multiply Divide Tally Counter represented by a labeled block in FIG. 1b controls the type of cycle, that occurs, during multiply and divide operations, as described below. The Execution Timers via the Mixing circuits, control the data processing throughout the Machine. The particular Execution Timer controlling during a particular type of operation is that Execution Timer related to the particular operation, for example, during an ADD operation, the ADD Execution Timer takes control.

INSTRUCTION REPERTOIRE OF THE MACHINE In order to obtain a solution for a given problem, a Program is provided comprising a sequence of Instructions, and the respective Operations, carried out under control of these Instructions, in the sequence in which they appear `or determined by intermediate results produce the desired solution of the problem. Both the Program and the numeric data for the problem are stored in the machine, the programmer, designing the program so that the steps are carried out in the proper manner.

Before proceeding to the description of the Machine construction and operation a briefdiscussion of the Instruction Repertoire of the Machine will greatly aid in comprehending fully, the description which. later follows. As stated above, each Instruction is stored in a'coded permutation of binary 1 and binary 0 representations, each Instruction including 5 such bits to represent, by their permutations of binary l and binary O bit conditionseach of 32 operations, which are recognized respectively by the Operation Decoder whose outputs, respectively control circuits to carry out the particular Instruction so de-coded.

One such Instruction whose 5 coded binary 1 and binary 0 bit values are 00000, comprises STOP and TRANSFER. This Instruction controls circuits which o STOP the Calculator as soon as this Instruction is read from Memory. When the Calculator, is again started up, by the operator, the execution of this STOP and TRANSFER Instmction is not completed and the Program transfers, so that Instruction, at the Memory Address, specied by the Address part, of the STOP Instruction. The Program of Instructions will then continue sequently, from this last Address.

The Instruction TRANSFER Whose binary l, binary 0 code representation is 00001 causese the NEXT Instruction to be taken from THAT Memory Address, specified by the Address part, of this TRANSFER Instruction. The Program of Instructions, then continues, Address number by Address Number sequentially, from this last Address.

The Instruction, TRANSFER ON AND RESET OVER FLOW abbreviated TR OV whose code representation 00010, will, if the Overflow indicator is ON, as the result of a previous operation, cause the Program to TRANS- FER THE Instruction, at the Memory Address, specified by the Address part, of the TR OV Instruction. The Overflow Indicator is reset, upon the completion of this Instruction. It the Overow Indicator is OFF, and this TR OV Instruction occurs, the transfer is NOT executed.

The Instruction TRANSFER ON PLUS abbreviated TR-l- Whose code representation is 00011, will if the Sign of the word in the Accumulator Register, is positive, cause the Program to transfer to the Instruction at THE Memory Address specified by the Address part, of the TR+ Instruction. If the Sign of the Word in the Accumulator Register, is negative, the transfer is NOT executed. It is to be particularly noted, that a positive zero value stored in the Accumulator Register is treated as a positive word, while a negative zero value stored therein, is regarded as a negative word.

The Instruction TRANSFER ON ZERO, abbreviated TR ZERO, whose code representation is 00100 will, if the value of the number stored in the Accumulator Register, is Zero, cause the Program to transfer to THE Instruction, at the Memory Address, specified by the Address part, of the TR ZERO Instruction. If the value of number stored in the Accumulator Register is not zero, the last transfer is NOT executed.

In order to clarify the description, certain of the following Instructions will be described by means of numerical examples. In these examples, the binary point will be arbitrarily considered as occuring in a position between the P and the 1 orders, of the Adder and of the Accumulator Register. In other words, bits 1 through 35, are to the right of the binary point, while bits P and Q, re to the left of the binary point. In most of the numeric illustration, only 3 or 6 bits, that is binary digits, are illustrated, merely to limit the number of bits to be considered, the modus operandi remaining the same as it would be for a full word of 36 bits or a half word of 18 bits.

The Instruction ADD whose code representation is 01001 causes the number, in THE Memory Address, specified by the Address part, of the ADD Instruction to be added, to the number stored in the Accumulator Register. The sum, appears in this Accumulator Register, as will be seen from the description below, while the word, at the specitied Memory Address, remains unchanged. The number Read from Memory at the Address specied may be either a full or a half word and, if a half word is specied, it is added, in alignment with the contents of the left half of the Accumulator Register (bit positions 1 through 17) but the sum, which appears in the Accumulator Register is of course the sum of the full Accumulator contents plus the half Word value. If

ths addition produces carries, to the left of the binary point, which, as stated above, lies to the left, of the 1 position, the overflow portion of the sum, appears in the two positions P and Q, to the left of the binary point and the Overflow Indicator, is turned ON.

Number from Accumulator Register Accumulator Register Memory Before Operation After Operation 011 +00. 011 +00.110 011 00. 011 00. 000 010 00. 010 -00. 100 010 +00. 010 +00. 000 110 00. (lll +00. 011 000 +00. 000 +00. 000 110 +00. 110 +01. 100* 110 +11. 110 +00. 100* *Overflow AIndicator is turned ON if it is not already ON.

The IInstruction RESET AND ADD, abbreviated R ADD, whose code representation is 01010 causes the contents of the Accumulator Register to be replaced by the word at the Memory Address indicated by the Address part, of this R ADD Instruction. If a half word is specified, it appears in the left half of the Accumulator Register, that is in bit Ipositions 1 to 17, 'inclusive while the right half of the Accumulator Register is Reset to 0. The `overow positions, of the Accumulator Register, are always reset to O, by this Instruction. Various examples of this Instruction are as follows:

Number from Accumulator Register Accumulator Register Memory Before Operation After Operation 011 anything +00. 011 011 anything 00. 011 000 anything +00. 000 000 anything 00. 000

follows:

Number from Accumulator Register Accumulator Register Memory Before Operation After Operatlon 01o +00. on i +oo.1o1 l0 +00. 011 +00. 101 010 -00. 011 -O0. 001 110 00. 110 -00. 000 110 +00. 110 +01. 100* *Overflow rIndicator is turned ON if it is not already ON.

The Instruction SUBTRACT, abbreviated SUB Whose code representation is 00101 is the same as the ADD Instruction, except that THE Sign of the number, read fromV the designated Memory Address, is CHANGED, before this number is added, to the number in the Accumulator Register. In other words, the subtraction is performed algebraically, with the .result being stored in the Accumulator Register and the number, in Memory, re-

10 maining unchanged. Various examples of this Instruction are as follows:

Number from Accumulator Register Accumulator Register Memory Before Operation After Operation *Overflow -Indicator is turned ON if it is not already ON.

The Instruction RESET AND SUBTRACT, abbreviated R SUB whose code representation is 00110 causes the number, at the specified Memory Address, to be placed, in the `previously Reset Accumulator Register, ex cept that the Sign of the number from Memory is changed. This Instruction is equivalent `to Resetting the Accumulator Register and then performing the operation of subtract. Various examples of this are'as follows:

Number from Accumulator Register Accumulator Register Memory Before Operation After Operation 011 anything -00. 011 011 anything +00. 011 000 anything -0O. 000 000 anything +00. 000

The Instruction SUBTRACT ABSOLUTE VALUE, abbreviated SUB AV, whose code representation is 00111 causes an operation, similar to the ADD Instruction, except that the number, .read from the speciedMemory address, is treated as negative regardless of its actual Sign. Various examples of ythis Instruction are as follow-s:

Number from Accumulator Register Accumulator Register Memory Before Operation After Operation *Overflow Indicator is turned ON if it is not already 0N.

The Instruction NO OPERATION, abbreviated NO OP causes nothing to happen. The result of this Instruction is to progress the Program to the NEXT Instruction. The Address and the Sign of this Instruction, may have any values, being without significance since this Instruction causes nothing to happen. This Instruction, however, inds utility, where it is desired to, in effect, delete an Instruction from a Program. In such an event, the substitution by the Programmer `of a NO ORERATION Instruction for some other Instruction, allows the machine, to proceed, WITHOUT requiring the substitution lof another Instruction, in place of the deleted Instruction.

The Instruction STORE Whose code representation is 01100 causes the word, in the Accumulator Register to be stored, in Memory at the Address specified by the Address part, of the STORE Instruction. The contents of the Accumulator Register are not changed by this operation, but the Word, which was originally stored at THE Address in Memory, is lost by this operation. The bits, in the overflow positions of the Accumulator Register that is bits P and Q, are NOT included, in the STORE operation. When a full word Address is specified, by the Address part, of the STORE Instruction, the Sign and the 35 bits, to the right, of the binary point, that is, bits 1 through 35 of the Accumulator Register are stored at the specied Address in Memory. When a half word Address is specified, by the Address part of the Instruction, the Sign, and bits l to 17, inclusive only, of the Accumulator Register, are stored in the half word Address specified in Memory.

The Instruction STORE ADDRESS abbreviated STORE A whose code representation is 01101 causes 12 bits at the extreme right of the half word, in the specified Memory Address, to be REPLACED, by the 12 bits of the 6 through 17 bits of the Accumulator Register of a right half word or the 12 bits of the 24 through 35 bits of a right half Word.

The remaining 5 bits of the half word (representing the operational portion of the Instruction in this half word) stored in Memory at the specified Address and its Sign, are left unchanged. The contents of the Accumulator Register are not changed by this operation. It should be particularly noted that this Instruction is used, with half word Addresses, only.

An example of this Instruction STORE ADDRESS is as follows:

Accumulator Register +0000 111 000 111 000 111 000 111 000 Selected Memory Address Before .01 010 101 010 101 010 Selected Memory Address After .01 010 000 111 000 111 (The underlined portion indicates those bit positions affected.)

The Instruction STORE NUMBER FROM MQ, abbreviated STORE MQ whose code representation is 01110 causes the number in the MQ to be stored, at the Memory Address speci-fied by the Address part of the Instruction. The contents of the MQ are not changed by this operation, but the number, which was originally stored, at the specified Memory Address, is lost. lVhen a full word Address is specified in the STORE MQ instruction, the entire content of the MQ are stored at the Memory Address specied. When a half word Address is given, the left hand 18 bits (The Sign and bits 1 through 17) in the MQ are stored at the half word Memory Address.

The Instruction LOAD MQ Register, abbreviated LOAD MQ whose code representation is 01111 causes the number in the MQ to be replaced by the number from the Memory Address specified by the Address part, of the Instruction. This Instruction may be used with either full or half word Addresses. If a half word is specified, it is entered into the left half of the MQ (bit positions, S, and 1 through 17) and the right half of the MQ is reset to zero. Various examples of this Instruction are as follows:

Word from MQ Register Before MQ Register After Memory Operation Operation 011 anything 011 .011 anything .011 000 anything 000 The Instruction MULTIPLY abbreviated MPY whose code representation is 10000 causes the Accumulator Register to be reset to and the number, at the Memory Address specified by the Address part, of the MULTIPLY Instruction, (the multiplicand) is multiplied by the number in the MQ (the multiplier). The more significant 35 bits, of the product, appear in the Accumulator Register, the less significant 35 bits appear in the MQ. The Signs, of both the Accumulator Register and of the ,1Q are set, to the Sign of the product, according to the algebraic Sign rules. When a negative number is multiplied by a positive number and either part, or the whole of the product, is zero, this zero is given a negative Sign.

The multiplicand from the specified Memory Address, may be either a full or a half word. If a half word is specified, the MULTIPLY Instruction operates, as though it were a full word, with 1S zeros on the right. The MQ is always treated as if it contained a full word, even though a half word has just been piaced in it. Thus, if a half Word has been put into the MQ and a MULTIPLY Instruction is given, with a half word Address, the product would have 34 significant bits and would appear in bit Number from MQ Before Accumulator MQ After Memory MPY Register After MPY MPY The Instruction ROUND whose code representation is 10011 carries out an operation which, if the most significant bit (in position l) of the MQ contains a binary 1, the value of the number in the Accumulator Register is increased, by a value equal to 2-35.

When the Instruction given is a ROUND Instruction :the number, in the Address portion, has no significance, thus any values .may be used in that portion. Various examples of the ROUND Instructions are as follows; recalling that with the 5 bit capacity .illustrated the 5th bit assumes .the identity of the least significant bit which corresponds 'in operation to the 35th bit of the Accumulator Register.

Accumulator MQ Before Accumulator MQ after Register Before Round Register after ROUND Round ROUND +00. 01 100 l. 10 000 +0001 101 10 000 +0001 +.01 000 +00. 01 100 -I- 01 000 +0011 lll .10 000 +0100 000* l0 000 00.10 011 10 000 00.10 100 10 000 *Overow `Indicator goes ON if it is not already ON.

The Instruction MULTIPLY and ROUND abbreviated MPY R, whose code representation is 10001 carries out a regular multiply operation which is followed, yby a round operation. Various examples of MULTIPLY AND 'ROUND operations are as follows:

Number From MQ Before Accumulator MQ after Memory MPY R Register after MPY R MPY R The Instruct-ion DIVIDE, abbreviated DIV whose code representation is 10010 performs the basic operation -of dividing a 70 bit dividend by a 35 bit divisor to produce a .35 bit quotient and a 35 bit remainder. Before the divide operation is performed, the more significant 35 `bits lof the dividend are placed in the Accumulator Register `and the less significant 35 bits of the dividend are placed in the MQ. Then, as the DIV-IDE Instruction is given, its Address specifying the Memory Address of the division. Upon completion of the divide operation, the quotient, appears Iin the MQ and the remainder appears 1in the Accumulator vRegister as will be obvious from fthe detailed descrip-tion of the divide operation given later. The sign of 4the dividend is stored, in the Sign position of the Accumulator Register. When the DI- VIDE Instruction is given, `the Sign of the MQ -is ignored. The less significant 35 bits of the dividend which are 13 stored in the MQ are considered as increasing the magnitude of the more signicant half of the dividend (that is :the 35 bits stored in the Accumulator Register). As a result -o'f the divide operation, the Sign of the quotient stored inthe MQ is that given `by the `algebraic Sign rule.

1d the Sign of the Accumulator Register. The Sign of the Accumulator Register and the Overflow Indicator are NOT aected by this operation. Again the number of places which shift can take place, cannot exceed 255 and again, this is almost Without signii'icance if a shift of 5 The Sign, of the remainder, remains the saine `as lthat of more than 70 places is required. The Sign of this Inthe loriginal dividend, the DIVI'DE Instruction may be struction has no signiiicance. The following examples given, with either full or half word Addresses. Half of the Instruction L RIGHT are given with an assumed Word divisors are considered as if they Were full Words, capacity of 9 -bits for the Accumulator Register and 7 bits with the `17 significant bits, in .the positions, immediately 10 for the MQ. to the right, of the binary point, and the remaining 18 bit positions (to the right) conatinirig zeros. IF the H DIVIDEND IS EQUAL To or GREATER than the Instruction? Original Contcrits of- Final Contents of- DIVISOR, SO THAT 'the ABSOLUTE VALUE of the A R M Ac R M QUOTTENT isi er GREATER, (assuming we are worir- C- eg' Q- c' g- Q' ing in fractional Values) the CALCULATOR STOPS, as Y n A illustrated below. In the following examples of `a divide Tiii iiitli 313313 1333338881 1:01813 .ope-ration, the Memory Address, the Accumulator Regis- L RIGHT 0000 +00. 001011 010010 +00. 001011 010010 Ier. and the MQ7 are illustrated as they had a Capa-City Iiiiigrii gigi) iijgiiigii jgiggig -iiiigi Iigflgiii of only 5 bits, to the right of the binary point, instead 20 lOf the aCtUal bits. *Address given in the decimal equivalent of the binary number.

Number from ACC. REG. MQ Before Memory Before DIV. DIV ACC RE G. MQ after (divisor) after DIV. DIV

(remainder) (quotient) (dividend) .10 110 +00. 01 10i +.01 0.1.0 +00. 01 000 .10 011 10 110 +00. 01 10i 01 010 +00. 01 000 i0 011 .01 100 00. 00 110 1i 011 00. 00 011 +.i0 010 11 101 +0010 010 .00 100 +00. 00 000 +.10 100 +.11 100 00.00 000 +.1i 001 00.11 001 00 000 00 000 +0001 100 00 000 calculator stops: DIV CHECK 01 000 00.01 010 .01 011 Caiculator stopsl; DIV CHECK The Instruction LONG SHIFT LEFT, abbreviated L The Instruction SHIFT ACCUMULATOR LEFT, ab- LEFT Whose code representation is 1010() causes the con- 35 breviated A LEFT Whose code representation is 10110 tents O'f the Accumulator Register and of the MQ to be causes the contents of the Accumulator Register to be shifted, to the left, Iby a number of spaces, speci/lied by shifted, to the left, by the number of places specified by the Address part of Ithe Instruction. The bit-s, which are the Address part, of the instruction. The emptied places, .shifted to .the left come from the MQ register .and apyto the right, in the Accumulator Register, are lled With pear, at the right `side of the Accumulator Register. 40 zeros, and the Sign of the number, in the Accumulator When the L LEFT Instruction is given, the Sign of the Register is not changed. THE LAST TWO BITS Accumulator Register is changed, if necessary, to con- SHFTED PAST THE BNARY PQNT, APPEAR IN form to the Sign of the The Sign of .the MQ is not THE GVERFLOW POSITIONS 0f 'the ACCuinUlatOl affected :by this operation. The Overiiow Indicator is Rgisel, and ANY BTS SHFTED BEYOND THESE turned ON, .any bits, are shifted tothe left, that is any OVERFLOW PSITNS ARE DSCARDED. AS the binary 1 bits, are shifted, to the left of the binary point BTS ARE SHFTED, PAST the BNARY FNT, in the IAccumulator Register. The number of places THEY ARE, SAMPLE) and a hillary 1 S S0 shifted, shifted cannot exceed 255, but of course, this number, is 'the OVGIOW I-ldcof S UHF-5d N- This COndOn, almost without signiiicance, since a shift of 70 will piomay lb@ detcd, by a Subsequent TRANSFER GN duce all zeros, in the Accumulator Register .and in the OVERFLOW Lls'fllil Again, the Humber 0f PCeS MQ. The Sign cf this Instruction, has no significance, called for byv such a shift, cannot exceed 255. The Sign The 'following examples of L LEFT assume that the Acof this Instruction has no significance. The following cumulatcr Register has a 9 bit capacity and the MQ a 7 62133113155 'Of A LEFT Instructions assume that the Acbt capacity, cumulator Register, has a capacity of 9 bits.

Original Contents of- Final Contents of- ACC. REG. Ac0.Reg. Overow Overflow Instruction* Instruction* Before after Indicator Indicator Accumulator MQ ACC, MQ Operation operation Before After Reg. REG. G0 i sa, una :it L LEFT 0003 +00. 001011` 010010 +01.0110i0 010000"t Ar IFT 000.3 3101001011 oif Si? 8g L LEFT 0003 +00. 001011 010010 01.011010 .010000** A LEFT 000i +00. 001011 +00. 010110 ON ON L LEFT 0000 -1-00001011 .010010 00.001011 .010010 A LEFT 0000 00. 001011 11.000000 OFF ON L LEFT 0000 00.001011 010010 +00. 000000 +.000000** A LEFT 0037y +00. 001011 +00. 000000 OFF ON ALEFT 0000 +00. 001011 +00. 001011 OFF OFF *Address is given in the decimal equivment of the binary number. Overflow Indicator is turnedON if it isnot already ON. :'Ihe abddress part, of the Instruction, is given, in the decimal equivalent The Instruction LONG SHIFT RIGHT abbreviated L 11 um; igiers'iuary number Addresses, all other columns contain binary RIGHT whose code representation is 10101 causes the contents of the Accumulator Register and the MQ to be The Instruction SHIFT ACCUMULATOR RIGHT shifted, to the right, by the numberA of places specified by abbreviated A RIGHT whose code representation is the Address part of the Instruction. Bits which are 10111 causes `the contents of the Accumulator Register shifted to the right, out of the Accumulator Register, are to be shifted, to the right, by a number of places specified shifted, into the leftmost positions (exclusive of Sign) by the Address part, of the Instruction. The empty the MQ. When a L RIGHT Instruction is' given, the places, to the left, in the Accumulator Register, `are iilled ign of the MQ is changed, if' necessary, to conform to 75 with zeros, and the bits which are shifted, beyond position Instruction* Accumulator Register Accumulator Register After Operation Before Operation A RIGHT 0003 +11. 001011 +00. 011001 A RIGHT 0003 00.001011 -00. 000001 A RIGHT 0037 +00. 001011 +00. 000000 A RIGHT 0037 -00. 001011 +00. 000000 A RIGHT 0000 +00. 001011 +00. 001011 *The Address part, of the Instruction, is shown in the decimal equiv- :filent of the binary number Address; all other numbers are in binary orm.

Before proceeding to the description of the Operation of the various units comprising the Machine, and in particular the CALCULATOR, the detailed circuit diagrams of various standard circuit components employed as logical AND circuits, logical OR circuits, or as triggers, inverters, cathode followers, Delay Units, etc., will be described in detail, with reference being made to their labeled block symbols. Thereafter, properly labeled block symbols, representative of these respective cornponents, will be used in the various figures, of the drawings, it being understood that the contents lof the respective blocks comprise identical or similar detailed circuitry. It is deemed obvious that those skilled in the art can, as required by operation conditions make the necessary changes in the values of the condensers, resistors, inductances, tube types voltages etc., to provide the most efficient operation under the particular electrical conditions that are encountered. The values herein given are those which have been found most efficient in an actually constructed and operated Electronic Data Processing Machine, including the novel Calculator of instant application.

Before proceeding to the description of the Counters, Registers, Control and Mixing Circuits, a detailed description of several standard component circuits employed, such as logical AND circuits, logical OR circuits, triggers, inverters, cathode followers, and delay elements, etc. will be given. The properly labeled block symbol representative of these respective components, as they appear in the various figures of the drawings, will thus be understood to comprise identical or similar detailed circuitry, it being obvious to those skilled in the art that changes in the values of components and in the particular assemblages would be made to provide the most efficient operation under the electrical conditions that are encountered. The values given are exemplary only.

A description of standard components of which the present invention maybe embodied is found beginning at column 27 of said Haddad et al. Patent 2,974,866. A computer system within which the adder sub-system in accordance with the present invention may be used is described in detail in said patent, between column 36, line 75 and column 114, line 48 thereof.

Referring now to FIG. 7d, which illustrates an exemplary circuit representative of the Adder orders P and Q, the input, from the corresponding order of the Accumulator Register, passes through True-Complement control circuits, identical to those described above for the Adder orders 1 through 35, blocks 741:1 through 747a of FIG. 7d, corresponding to the blocks 711:1 through 71'7a of FIG. 7c. Thus, it is seen that signals, on line A of the Adder per se, in FIG. 7d, represent either True or Complement, binary 0 or binary 1 value manifestations, from corresponding orders of the Accumulator Register. Likewise, when input terminal 2 (FIG. 7d) is positive, to represent a binary 1 Carry, it is fed via the line CARRY IN, to line B of the Adder, per se. The operation of the remaining circuitry of FIG. 7d, is that of a half Adder, having two inputs. If there are binary l inputs, that is positive signals, on both lines A and B, simultaneously, the resulting SUM is zero, with a Carry of a binary 1. If there is a binary 1 present on line A, but a binary 0 on line B, the result is a binary l SUM and a binary 0 Carry. Likewise, if there is a binary 0 on line A, but a binary 1 on line B, the result is a SUM of binary l and NO Carry. The final condition, if there are binary Os on both lines A and B, produces a SUM of binary 0, and a Carry of binary 0. The output -of the AND circuit 748:1 is positive, only when it receives two positive inputs, so that if both lines, A and B, have binary ls, the output of the AND circuit 748a goes positive, and via a cathode follower 749:1, drives the line CARRY OUT, positive, which is applied to terminal 7. When a binary 1 is present, on either line A or B, or both, the output of the OR circuit 75211, goes positive, and conditions the AND circuit 753:1. If a Carry output, did occur, which signifies that both lines A and B contain binary 1s, the positive output of a cathode follower 749e, signifying a binary 1, is inverted, by an inverter 750:1, and passed via a cathode follower 751a to an AND circuit 75311. Thus, if both lines A and B contain binaiy ls, the result is a Carry output, but the Sum output is BLOCKED, from passing through the AND circuit 753:2. However, if a binary 1 is present on line A or B, there still is a positive output, from the OR circuit 752a, and, since there isV NO Carry, the inverter 750:1 cannot invert, a plus input, since there is none, so that the AND circuit 753:1 IS conditioned, and a positive output from the OR circuit 752:1 passes through this conditioned AND circuit 753g, and the cathode follower 754,51, to the line SUM OUT and thus to terminal 8.

Thus, it is seen that if binary ls are present on both lines A and B, a binary 1 Carry output is developed, but the SUM output is a binary 0. If a binary 1 is present, on line A or B, a binary 0 Carry output is developed, but the SUM output is a binary 1. If binary Os are present on both lines A and B, then both output lines, the SUM OUT and CARRY OUT, remain negative to signify binary Os.

ACCUMULATOR REGISTER Referring again, to FIG. 1d, a block diagram of the Accumulator Register is illustrated therein. It is to be noted that the Sign order (see also FIG. 7e) is different from all the other orders of the Accumulator Register (see FIG. 7f).

The Q, P and 1 through 35 orders, are alike and an exemplary order is illustrated in FIG. 7f.

Each order of the Accumulator Register comprises a Delay Unit, of the type as described above, and as indicated (FIGS. 7e and 7f, respectively), there are two sources of HOLD voltage namely, the line HOLD ACC (S) (FIG. 7e) and the line HOLD ACC (FIG. 7f).

The line HOLD ACC (S) for the Sign order is connected to terminal 2 (FIG. 7e), while the line HOLD` ACC (FIG. 7j) is connected to terminal 7 and feeds to all the Accumulator Register orders Q, P and 1 through 35. These orders, Q, P and 1 through 35 each receive said input, from corresponding orders of the Adder and these same orders have outputs, which feed to respective terminals 3 (FIG. 1d) of the True/Complement controls, described above, of corresponding orders, of the Adder.

Order 35, of the Accumulator Register (FIG. 1d) receives an input via its terminal 4, 'from the MQ order 1 (FIG. 1g) which is effective, when the control line MQ i? (l) TO ACC (35) feeding to terminal 3 of this 35th order (FIG. 1d) goes positive (see also FIG. 7f) to per- Init the contents of MQ order 1 to be introduced into the Accumulator Register 3S. On a LONG SHIFT LEFT Instruction or a DIVIDE Instruction, as described below, this signal MQ (1) TO ACC (35) is applied to terminal 3 of the 35th order, instead of SHIFT ACC LEFT (FIG. 71). The outputs of corresponding orders of the Adder, are gated to the Accumulator Register as the line ADDER TO ACC connected to the respective terminals 1 (FIGS.

1d and 7i) goes positive. A signal on this line (FIG. la) also causes the line HOLD ACC, to go negative, at the sarne time, as described above, in connection with FIG. la. The holding of the Accumulator Register may also be shifted, to the right, or to the left, by positive signals on the respective lines SHIFT ACC RIGHT connected to the respective terminals 5, or line SHIFT ACC LEFT connected to the respective terminals 3 (FIGS. ld and 7f), this shifting occurring, at the rate of one order, for each microsecond that the respective lines are positive. The signals on the lines SHIFT ACC RIGHT and SHIFT ACC LEFT (FIG. la) also respectively cause the line HOLD ACC to go negative (see also FIG. 7i).

It should be noted that the outputs at respective terminals 8 of the Accumulator Register orders feed to an input terminal 4, of the next higher order (FIG. ld) and also to an input terminal 6, of the next lower order. It is these output signals, which are gated to the respective Delay Units, during a SHIFT ACCUMULATOR LEFT or a SHIFT ACCUMULATOR RIGHT operation, as the case may be, or during a LONG SHIFT LEFT or a LONG SHIFT RIGHT operation. The output of the Q order shifts to the right only, so that in FIG. 7f, the line SHIFT ACC LEFT is not used, in the Q order.

The output of Accumulator Register order 35, besides feeding to order 34 also feeds to terminal 3 of the MQ 1 order (FIGS. 1d, 1g). The orders S and 1 through 35 of the Accumulator Register also have outputs (FIGS. 1d and 1e) which feed to corresponding orders of the Memory Buss Switches, described below. As the Accumulator Register is shifted left, the output of the 1 order is connected to the MIXING CIRCUITS (FIGS. 1d, le, and lb) and thence to the Overow Trigger (FIG. 1b) as described above. Therefore, if a binary 1 is stored in the Accumulator Register 1 order, and the Accumulator Register is shifted to the left, one order, an Overow automatically results.

Referring now to FIG. 7e, which illustrates the Accumulator Register Sign order, again the basic storage element is a Delay Unit `designated as 764m The condition of the Delay Unit is dependent upon the binary 1 or binary character of the inputs, 'from either one of two sources. One is the recirculating feed back, feeding from the output of the Delay Unit and passing through the AND circuit 761g, provided the line HOLD ACC (S) connected to the terminal 2, is positive, to thereby condition this AND circuit 761a whose output then passes, via an OR circuit 7 62a and a cathode follower 763:1, to the input of the Delay Unit 76411.

On occasions, When it is necessary to put a positive Sign indication into the Delay Unit, that is, a holding of a binary 0, the HOLD ACC (S) voltage only, is made negative (see inverter 116 and cathode follower 117 of FIG. 1a) so that the line HOLD ACC (S) of FIG. 7e is rendered negative, and thus, regardless of what was formerly stored in the Delay Unit, the Delay Unit output then goes negative, which need not be recirculated, since a negative output IS produced by the Delay Unit unless it is forced to produce a positive output, which positive output, must be recirculated to be sustained, all as described above under STANDARD COMPONENTS.

However, when it is necessary to enter a negative Sign, into the Accumulator Sign order (a binary 1) a positive signal is fed directly into the OR circuit 762:1 (FIG. 7e) via input terminal 1, to line TO ACC (S) implying ES Minus Sign TO ACC (S) order. The eiect of this positive input to this OR circuit 762e, which passes directly via the cathode follower 763@ to the Delay Unit 76401, even though the AND circuit 761a is operative for feed back, is to inject a binary l, that is Va positive signal, into the Delay Unit, regardless of what was there previously. The recirculating loop [of the Delay Unit is NOT broken yat this time. Thus, if a binary 1, was formerly stored in the Delay Unit, it is recirculated, in `an attempt to again store a binary 1, which merely results, in a binary 1 being stored (if a binary 0 is stored, no recirculation is produced, since none is required). The output of the Sign position,

via line ACC (S) to terminal 3, is POSITIVE to indicate the storage of a negative Sign and conversely if NEGA- TIVE to indicate a positive Sign. The output terminal 3, as indicated in FIGS. 1d and 1e is connected to terminal 2 of the Memory Buss Switches, order S, described below and also is connected, as shown in FIGS. 1e and 1a to the Sign Mixer circuits, described above in connection with FIG. 5c of said parent patent.

Referring to FIG. 7f, there is illustrated an exemplary circuit representative of the Accumulator Register orders Q, P, and 1 through 35. It may be noted (see FIG. 1d) that input terminals 5 and 6, of the Q position, are NOT used, so that consequently, the AND circuit 773e (FIG. 7j) and is corresponding output to the OR circuit 775a, are NOT empioyed, in this Q order. The circuitry of these orders is somewhat similar to the circuitry of the orders of the Memory Register, described above, in that a Delay Unit 777a (FIG. 73) comprises the storage element, per se, of the respective orders. As ilustrated in FIG. 7J, this Delay Unit 7l7a, may receive an input, via one of four AND circuits. This Delay Unit may receive an input, as its output is recirculated, via an AND circuit 77411, provided line HOLD ACC, which is connected to terminal '7, remains positive, thus conditioning this ANI) circuit, whose output passes via an OR circuit 775'a, and a cathode follower '776e to this Delay Unit 777:1. The signal on the line HOLD ACC, is of course, driven negative, as described above, whenever any SHIFT LEFT or SHIFT RIGHT signal is given, and ALSO when the holding of the Adder is being gated to the Accumulator Register. The effect of the interruption of this HOLD signal is effectively to erase, whatever is already stored in the Delay Unit, since only a binary zero can exist with this AND circuit 774e de-conditicned.

Referring to the AND circuit 773e of FIG. 7f, this receives input signals via line SHIFT ACC RIGHT connected to terminal 5, and via line ACC (N +1) OUTPUT connected to terminal 6, this line comprising the output, from the next higher order of the Accumulator Register. Upon a coincidence of two such positive inputs, the output of the AND circuit 773g goes positive, and via the OR circuit 775a and the cathode follower 776:1 applies a positive signal to the Delay Unit 777er. Thus, Whenever a signal of 1 microsecond duration is given, calling for a SHIFT ACC RIGHT operation, the output of the next higher order of the Accumulator Register is gated via this AND circuit 773e to the Delay Unit 777er. At the time that the line SHIFT ACC RIGHT, goes positive, the line HOLD ACC, is negative, and is thus eifective, to erase the former holding of the Delay Unit. At the end of the 1 microsecond period, the line HOLD ACC, again becornes positive, to HOLD the newly stored bit of information, which was received from the next higher order of the Accumulator Register. If the signal on the line SI-IET ACC RIGHT is of a sufficient duration, say several microseconds, a shift from the next higher order of the Accumulator Register occurs, during each microsecond, the line HOLD ACC remaining negative during that period. Thus, for each microsecond that the line SHIFT ACC RIGHT is positive, a bit of information, is successively shifted, one order, for each such microsecond, to succeeding lower orders vof the Accumulator Register. It is an inherent characteristic of a Delay Unit such as 1S Delay Unit 777a, as described above, which allowsV an input signal to arrive, at the Delay Unit input, at the same time an output signal is being emitted, by this Delay Unit, indicative of what was formerly stored in that Unit.

The AND circuit 772a serves a function, similar to that of AND circuit 773a, except that it is for SHIFT LEFT. Here, an input signal on terminal 3 is applied to line SHIFT ACC LEFT to condition this AND circuit 772:1, while the output of the next LOWER order, of the Accumulator Register, is applied via terminal 4 to line ACC (N-l) OUTPUT and this output, from the next LOWER order, is passed via this AND circuit 77251, the OR circuit 775a, and the cathode follower 776a, to the Delay Unit 77741. Again, a shifting of a bit of information, to a successive order of the Accumulator Register (shifting to the left) occurs, for each microsecond that the line SHIFT ACC LEFT, is positive, line HOLD ACC remaining negative during that time.

The AND circuit 77111 receives inputs from correspending Adder order SUM outputs, via the terminal 2, feeding to the line SUM OUTPUT. If this AND circuit 77M is conditioned, by a positive voltage on line ADDER TO ACC connected to terminal 1, which may be either an E/R4 (DI) or an E/RS (DI) signal (see Timing Diagram FIG. 6a-e) then the SUM OUTPUT is gated through this AND circuit 77Ia.

Thus, upon coincidence of two positive inputs, the output of this AND circuit 771:1, goes positive, and via the OR circuit 775a and the cathode follower 776e, feeds a positive signal to the Delay Unit 777a. If the SUM OUTPUT of the corresponding Adder order is a binary 0, this signal on the line SUM OUTPUT, is negative, and the signal input to the Delay Unit 777:1 is negative, to thereby store a binary 0. The output of the Delay Unit 777a, feeds via line ACC (N) which thus is representative of any of the outputs, for orders Q, P and 1 through 35, respectively, each of which feeds to a respective output terminal 8. Thus, it is seen that the output of the Adder may be gated to the Accumulator Register, and that the holding of the Accumulator Register, may be shifted, left or right, a shift occurring at a rate of one order per microsecond.

It should also be noted, as stated above, that the signal MQ (l) to ACC (35) which feeds to terminal 3 of the Accumulator Register order 35 (FIG. ld) on occasions, as described above, when the Accumulator Register and the MQ are being shifted jointly, to the left, as one register, the signal, on the line ACC (N-l) OUTPUT connected to terminal 4 (FIG. 71) is actually coming from the MQ 1) output (FIG. ld), While the signal to terminal 3 of the Accumulator Register 34 order, is actually the signal MQ (1) TO ACC (35) (FIGS. lg and ld).

There has also been described above, how signals on lines TO ACC (S) and TO ACC (8) Will cause a direct insertion of a positive or negative Sign, respectively, in the Accumulator Register Sign order. Whenever a regular SHIFT ACC LEFT signal is given, for a shift operation that does NOT include the MQ, as described below, then the line HOLD ACC, connected to terminal 7 of the Accumulator Register 35 order, is driven negative, as usual, and as the information is shifted left, since NO binary l, is shifted INTO the Accumulator Register order 35 from the MQ, then in effect, a binary is stored in this Accumulator Register 35 order. In other Words, if a signal called for a shift of 6 orders, and a binary l was present initially, in all Accumulator Register orders, then as the information is shifted left, binary Os are effectively stored, in the Accumulator Register order, and these binary Os are shifted left, so that at the end of the 6 step shift operation, the last 6 orders of the Accumulator Register, namely, orders 30 through 35, all contain binary Os.

The outputs of the Accumulator Register, via terminals 8, of the respective orders (FIG. 71) are positive, to rep- 2@ resent storage of binary ls and negative to represent storage of binary Gs. These signals are fed (except for orders P and Q) mainly to the Memory Buss Switches, as illustrated in FIGS. laf-and le.

Descriptions of the MULTIPLIER QUOTIENT REG- ISTER; MEMORY BUSS SWITCHES, timing of TRANS- FER, STOP AND TRANSFER, TRANSFER ON ZERO, TRANSFER ON OVERFLOW, TRANSFER ON PLUS, LOAD MQ, NO OPERATION, and ROUND operations are all given between column 118, line 63, and column 127, line 39 of said Haddad et al. Patent 2,974,866.

RULES GOVERNING ADDITION Before proceeding to a discussion of the ADD Timing Diagram, illustrated on FIG. 6k of said parent patent, a few of the rules for binary addition, as performed by this Machine, will now be stated. During an ADD operation, the factors are added ALGEBRAICALLY, so that if the Signs are UNLIKE, the value, stored in the Accumulator Register is Complemented to a ls Complement, and is added, in the Adder, to the True value of the number stored in the Memory Register. By such an addition of a Complement number to a True number, SUB- TRACTION is actually performed.

If, in this ADD operation, the Signs are UNLIKE, and the ls Complement of the value stored in the Accumulator Register is added, in the Adder, to the True value of the number stored in the Memory Register, and an END CARRY is produced, an elusive 1 must be added in order that a correct result be obtained.

Thus the following rules for ADD may be stated:

Rule 1.-If the Accumulator Register and the Memory Register Signs are ALIKE, add the Accumulator Register value, in True form, to the Memory Register True value.

Rule 2 If the Accumulator Register and Memory Register Signs are UNLIKE, add the ls Complement of the Accumulator Register value, to the Memory Register True value.

Rule 3.-If the Accumulator Register and the Memory Register Signs are ALIKE, the Accumulator Register Sign is left unchanged.

Rule 4.-If the Accumulator Register and the Memory Register Signs are UNLIKE and (a) If NO End Carry results, it is an indication, that the value in the Accumulator Register was the larger, and the SUM, now in the Accumulator Register, is in Cornplernent form. Therefore, it is necessary to Recomplement the present Accumulator Register factor and leave the Signvof the Accumulator Register, lUN-CI-IANGED. (b) If there IS an End Carry, it is an indication, that the value in the Memory Register Was the larger, so that the SUM, now in the Accumulator Register, is in True form, but an elusive l must be added to the result and the Sign, of the Accumulator Register, must be CHANGED.

ADD

Referring new to Timing Diagram for ADD, illustrated in FIG. 6k of said parent patent, itis seen, from kthe labeling, that during Instruction time, an I9 (DI) signal, gates a HALF word ADD Instruction, from Memory, via the Memory Buss to the Memory Register and, at Il0 (D1) time, this ADD Instruction is dumped from the Memory Register into the Instruction Register. The Operation Decoder, determining that the operation is ADD, causes the Control Circuits to emit a GO T O EXECUTE signal, at 1111 (D1) time, sending the Machine into an Execute cyc e.

During this Execute cycle, specifically at E9 (DI) time, as indicated by ALL the labeling in FIG. 6k of said parent patent for this signal, a FULL, an EVEN half word, oran ODD half word is Read, out of Memory, via the Memory Busses to the Memory Register, and at E11 (DI) time, a GO TO EX/RGN signal is emitted, sending the, Machine into an Exccute/ Regenerate cycle. The purposeI 2l of the Execute cycle, is to Read the FULL or HALF` Word, in Memory, into the Memory Register, preparatory to dumping this FULL or HALF word, into the Accumulator Register. The word Read, out `of Memory, is Read from THE Address, specied by the Address portion of the ADD Instruction. The Execute/Regenerate cycle is required so that the actual addition can take place. During this Execute/ Regenerate cycle, an E/Rl (D4) signal is emitted, as indicated by its labeling, for gating the holding or" the Memory Register to the Adder. The factor, in the Accumulator Register, is also gated to the Adder at E/Rl (D4) time, in True or in Complement form, depending upon the Signs ofthe tWo factors, as indicated by the labeling in FIG. 6k of said parent patent. If the Signs are ALEKE, the value in the Accumulator Register is gated, in True form, to the Adder, but if the Signs are UNLLKE, the value, in the Accumulator Register, is gated, in Complement form, to the Adder, either operation taking place, under control of an E/R1 (D4) signal. Thus, by passing the value from the Memory Register to the Adder, and the value from the Accumulator Register, in True or in Complement form, to the Adder, an actual addition takes place. Because of the inherent nature of the Delay Units of the Adder, Carries, throughout the Adder, are propagated at a rapid rate, and, therefore, if an END CARRY ensues, it occurs almost immediately.

If the Signs are ALIKE, and the Adder 1 order emits a Carry signal, it is an indication of an Overflow, and the Carry output, of the Adder 1 order, is gated to the Overr'iow trigger by an E/Rl (D4) signal, to turn ON the Overow trigger.

However, if the Signs are UNLlKE, a Complement of the value from the Accumulator Register, is gated to the Adder, and if an End Carry occurs from the Q order, under this latter condition, it is an End Carry and under Rule 4b, set out above, it is necessary to add an elusive 1 in the Adder 35 order, at approximately E/Rl (D4) time. After allowing 3 microseconds, for propagation of carries, which 3 microseconds provides a large safety factor, an

E/d (D1) signal is emitted, as indicated in FIG. 6k of said parent patent, to gate the Sum, from the Adder, to the Accumulator Register.

As described above, this Sum, may be in True or in Complement form. if the Signs are UNLIKE, and NO End Carry resulted, then under RULE 4a above, it is known that the data in the Accumulator Register is in Complement form. Therefore, it is necessary to Recomplernent the number, so that the final value, stored in the Accumulator Register, at the end ofthe ADD operation, is in True form. To produce this Re-Complement operation, an E/R' (D2) signal is emitted as indicated in FG. 6k of said parent patent for passing the holding of the Accumulator Register, in Complement form, to the Adder. At this time, there is NO other input to the Adder, so the etect is to merely pass information, through the Adder, in order to Complement the value. At E/RS (D1) time, a signal is emitted, to gate the Re-Complemented output ofthe Adder, to the Accumulator Register, so that the Recomplementing operation is complete.

If the original Sum gated from the Adder to the Accumulator Register was in True form, then there was a carry from the Q order and this Recornplementing operation is NOT required.

At E/Rtl (D1) time, the Accumulator Register Sign order is SET positive or negative, as required by the algebraic rules of addition. Thus, if the Signs of the Accumulator Register and the Memory Register, are UNLIKE, and an End Carry resulted, the Sign of the Accumulator Register is changed, as indicated by Rule 4b, above. Therefore, if the Sign of the Accumulator Register is positive, a negative Sign must be stored in the Accumulator Register Sign order, by `a 1 microsecond signal, occurring at E/ R10 time, labeled, as shown in FIG. 6k :of said parent patent TO ACC (8) whereby the Sign is changed, as described in connection with FIG. 7e, above 22. by injecting a binary 1 directly into the Sign order, a binary 1 indicating a Minus Sign. 1f the Accumulator Register Sign is negative, under the same conditions, the signal emitted at E/Rltl (D1) time, is labeled TO ACC (3) as illustrated in FIG. 6k of said parent patent, which as described above, renders the line HOLD ACC (S) of FIG. 7e, minus to thereby insert a binary O, in the Sign order of the Accumulator Register, which binary 0 is indicative of a positive Sign.

Thus, it is seen that if the Signs are UNLIKE, and if an End Carry -did result, the Accumulator Register Sign is changed. At E/Rlt (D2) time, the End of Operation signal is given, and the Instruction Counter is stepped, one count.

In the following examples of ADD operations, the Memory Register is illustrated as though its capacity was 4 bits only, to the right of the binary point, instead of the .actual 35, and the same is true of the Accumulator Register. Both Overow positions, respectively, are also indicated.

Accumulator Register and Memory Register SIGNS Accumulator Register +00. 0101 Memory Register 1101 Result in Accumulator Register. +01. 0010 Note: An Overflow occurred, beyond the binary point, and this is noted, by turning ON the OveroW trigger, as described above.

Accumulator Register 00.0101 Memory Register 0011 ResultinAccumulator Register- -00. 1000 Example 2.-Accumulator Register and Memor Re ister SIGWS UNLIKE; y g i Accumulator Register +00. 0101 Complexneuted Accumulator Register 11. 1010 Memory Register. 0111 C 00. 0001 Since End Carry add elusive 1 and change Sign (Rule 4b) Result m Accumulator Register. 00. 0010 Accumulator Register +00. 0101 Complcmented Accumulator Register 11. 1010 Memory Register 0011 NC 11. 1101 Since NO End Carry Result inAccurnulator Register. +00. 0010 Recomplemcnt Accumulator and leave Sign unchanged (Rule 4a) Accumulator Register- +00. 0101 Compton/rented Accumulator Register Memory Register.

11. 1111 Result in Accumulator Register- +00. 0000 NC Since NO End Carry Recomplement Accumulator and leave Sign 1mchauged (Rule 4a) 11. 1111 Since NO End Carry Result m Accumulator Register- -00. 0000 Recomplement Accumulator and leave Sign uuchauged (Rule 4a) In the examples, given above, Example 1A, illustrates a situation in which the Accumulator Register and the Memory Register Recomplemented, to contain a True 

6. IN A NOVEL BINARY PARALLEL ADDER DEVICE COMPRISING, IN COMBINATION, A PLURALITY OF ORDERS, EACH CONSISTING OF A FULL BINARY ADDER COMPRISING DIODE AND CIRCUITS AND DIODE OR CIRCUITS, AND EACH HAVING A SUM OUTPUT AND A CARRY OUTPUT, THE CARRY OUTPUTS OF EACH LOWER ORDER FEEDING TO THE CARRY INPUT OF THE NEXT HIGHER ORDER AND A PLURALITY OF HALF BINARY ADDER OVERFLOW ORDERS EACH COMPRISING DIODE AND CIRCUITS AND DIODE OR CIRCUIT AND EACH HAVING A SUM OUTPUT AND A CARRY OUTPUT, A LOWER ORDER CARRY OUTPUT FEEDING TO THE CARRY INPUT OF THE NEXT HIGHER HALF BINARY ADDER. 